The subject matter disclosed herein relates to memory, and more particularly to the use of a memory circuit using Dynamic Random Access Memory arrays.
Many different types of memory circuits can be used to compare input data (e.g., an input pattern or search data) against stored data (e.g., reference pattern(s) or a table of stored data). One example of such a memory circuit is a Content Addressable Memory (CAM). When a CAM determines a match between the input data and the stored data, it returns the address(es) of the matching data.
A two-state CAM (or Binary CAM (BCAM)) uses binary data consisting entirely of two states (0s and 1s) for comparing input data to stored data as shown in the exemplary two-state CAM truth table of FIG. 1A. The two-state CAM truth table (FIG. 1A) is of an XOR gate (Exclusive OR), wherein the output is “yes” for a match only if both the input state and the stored state are the same. Conversely, the output is a “no” for a mismatch if the input state does not match the stored state.
A three-state CAM (or Ternary CAM (TCAM)) uses data consisting of 0s and 1s as well as a third state known as a “no care” state (or “BX” state) as shown in the exemplary three-state truth table of FIG. 1B. The TCAM truth table (FIG. 1B) is also of an XOR gate (Exclusive OR), wherein the output is “yes” for a match only if (a) the input state and the stored state are the same, (b) the stored state is a “no care” state (BX) regardless of the input state (0, 1, or BX), or (c) the input state is a “no care” state (BX) regardless of the stored state (0, 1, or BX). Conversely, the output is a “no” for a mismatch if the input state does not match the stored state, except in the case where the input state or the stored state is a “no care” state (BX). In many cases, the input data is a stream of several bits, where each input bit must be compared to a stored bit in a CAM cell to determine if all of the bits match to provide a “yes” output.
Most conventional CAMs are built with static random access memory (SRAM) cells or Flash Negative-AND (NAND) cells, where a typical two-state CAM consists of two cells/bit and a typical three-state CAM consists of four cells/bit. Given the high speed of the cells, conventional CAMs allow for stored of information that can be retrieved rapidly. However, SRAMs and Flash cells operate at high power and can be expensive to produce. In addition, conventional CAM arrays for handling multiple bits are manufactured with the control circuitry (e.g., comparators) for comparing the input data and the stored data within the array, increasing the complexity and cost of the memory circuits, while restricting the flexibility of the CAM arrays.
BCAMs and TCAMs designed with three-dimensional (3D) packaging where multiple die are stacked together have been disclosed in, e.g., U.S. Pat. Nos. 8,513,791 and 8,576,599. This can improve system performance and reduce power consumption. In these designs, the vertical connections at the cell level reduce the resistivity between the CAM cell and the circuitry located in a different die. However, since one connection of 3D connections per cell is then required, or millions per die, this is difficult to manufacture.
Dynamic Random Access Memory (DRAM) is another type of memory that stores each bit of data in a separate capacitor where each memory point consists of a single capacitor and a single transistor per bit. DRAM is often used in personal computers as the main memory, e.g., in desktops, laptops, video game consoles, etc. The capacitor can be either charged (“1”) or discharged (“0”) with these two states representing the two values of a bit. Since the capacitors will always discharge, the capacitors are typically “dynamically” refreshed every millisecond. During the read cycles, typically done within 2 ns to 15 ns, the sensing elements of the DRAMs compare the voltage across each cell with the one stored in a reference cell to determine if a “1” or a “0” state has been programmed. Since DRAMs consist of volatile memory, it loses its data when power is removed and is therefore not suitable for secure elements, which store reference patterns (e.g, words or keys) in non-volatile memory (e.g., Flash or EEPROM).
As disclosed in, e.g., U.S. Pat. Nos. 6,331,961, 6,430,073, 7,016,211, 7,088,603, 7,307,860, 7,508,022, and 8,089,793, DRAM has been used in the design of CAMs or TCAMs, replacing conventional SRAMs with DRAMs. Since DRAM only requires only one capacitor and one transistor per bit, is less expensive than SRAM, BCAMs and TCAMs made with DRAM (i.e., DCAMs) are less expensive than conventional BCAMs and TCAMs made with SRAM. However, since DRAMs are typically slower than SRAMs, operate slower than conventional BCAMs and TCAMs made with SRAM.
The technologies and processes used to manufacture DRAM s are extremely complicated, expensive, and time consuming. Since DRAM cells are densely packed within bi-dimensional arrays, it is important to keep the packing density constant. Existing techniques for designing DCAMs include breaking the periodicity of the DRAM arrays, mixing DRAM cells with comparing circuitry since a comparator is employed in each cell to compare the bit of the input pattern with the corresponding bit of the reference pattern. As a result, these DRAM cells used in DCAMs are not packed the same way as traditional DRAM arrays, and cannot be produced without re-developing the DRAM manufacturing technology.
The discussion above is merely provided for general background information and is not intended to be used as an aid in determining the scope of the claimed subject matter.